The ramptime of an electrical signal is the time it takes for the signal to transition from one logic state to another logic state. For example a “rise time” is a time it takes for the signal to transition from a logic low level (such as a ground voltage, VSS) to a logic high level (such as a power supply voltage, VDD). A “fall time” is the time it takes for the signal to transition from the logic high level (such as VDD) to the logic low level (such as VSS). However instead of using the full-swing ramptimes defined above, to define ramptimes in terms of percentages of the full-swing voltage. For example, a 10%–90% ramptime (risetime) can be used to define the time required for a signal response to increase from 10% of VDD to 90% of VDD. A 30%–50% ramptime (risetime) is the time required for the signal response to increase from 30% of VDD to 50% of VDD.
In the design of advanced semiconductor integrated circuits, each semiconductor technology has a maximum ramptime limit for which all signals must meet in a design for that technology. If one or more signals generated within or by the integrated circuit design exceed the maximum ramptime limit, the design's performance will not meet its target performance or the design may fail to operate correctly.
The ramptimes of individual signals in a design impacts several design parameters. These parameters include signal quality and degradation. A signal transition preferably swings completely from one supply voltage level to the other supply voltage level. This swing can be reduced by an increase in ramptime. Ramptime also impacts Hot Carrier Induced (HCI) transistor degradation, which can affect circuit speeds and transistor lifetime. An increase in ramptime can increase power consumption of the integrated circuit, since a longer ramptime increases the short-circuit current that occurs when transistor devices switch states. An increase in ramptime can also lead to an increase to electromigration, which effects the lifetime of vias between metal layers on the integrated circuit. Increases ramptime can also increase crosstalk-induced noise and delay between the signals, which effects timing in the integrated circuit.
For these reasons, the ramptimes of signals generated within the integrated circuit should not exceed pre-defined technology ramptime limits. In addition to these pre-defined technology-based ramptime limits, there is a relative ramptime limit that is frequency-dependent. As the pulse width of a signal narrows with increasing frequency, the ramptime of the signal should also be reduced to ensure that the signal spends at least some time at the voltage supply rails.
Frequency-based ramptime limits have previously been set based on some criteria. For example, the ramptime for a clock signal on a clock net may be limited to a ramptime of ¼ or less of the clock cycle. A signal net may have a ramptime limit of ½ of the clock cycle. These ramptime limits are largely selected through intuitive thinking based on ideal waveforms and a desire for each signal to spend at least 50% of the time at a rail voltage level. However it may not be known whether such a ramptime limit is too conservative.
Cell libraries for semiconductor integrated circuit designs are usually characterized with an upper ramptime limit, which is usually larger than the technology-based ramptime limit, which is usually larger than the frequency-based ramptime limit. Thus, typical ramptime limits are fairly conservative.
Since fixing a ramptime violations tend to increase the chip size and the turn around time of the design process, it is not desirable to have a ramptime limit that is too conservative. Improved methods for setting ramptime limits are therefore desired.